Openings for System Level Verification Engineer

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Roles & Responsibilities:
    • Verilog and C/C++ coding a must
    • Makefiles, Perl scripting a must
    • Chip/full system level ASIC Verification skills, and debug skills a must
      • Debug using waveforms a must, Verdi source level debug a plus
    • Board level debug desirable
    • Experience working with AMD 64 architecture a great plus
    • Experience working with PCI-Express a plus
    • System level knowledge a must
      • System is defined as a test bench containing {CPU + GPU + multi-media engines + Southbridge} with hardware based coherency, hardware based transaction ordering
      • System could be a simulation test bench, emulation test bench or a board
      • System level knowledge/verification does not mean signal integrity checking, electrical checks, EMC checks, thermal checks, static timing analysis, lint checking
      • Tests will be written in C/C++, compiled for CPU and will be run on simulation/emulation/board unchanged
    • Block/unit level verification skills using OVM/UVM knowledge desirable, but not required
    • Experience working in AMD, Intel or other big SoC (system on chip) companies
    • Experience writing “assembly language tests”, “assembly level” debug
    • Experience with caches, coherency
    • Experience with “concurrent tests”
    • Experience working on board-level debug
Preferred Education:
B.Tech,BSc,MSc,MCA
Location:
Bay Area, California, United States
Area of Expertise:
Verilog, C/C++, Makefiles, Perl scripting
Experience:
5+ years.
Job Code:
BA-2018-190
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