Openings for SoC Verification engineer

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Minimum Qualifications:
  • Strong experience in creating test benches from scratch in System Verilog – UVM
  • Strong understanding of ARM architecture and AXI/AHB/APB
  • Demonstrable experience writing System Verilog assertions
  • Strong problem solving and debugging skill
  • Programming experience in C++(would be a plus), Perl and Assembly Algorithms and digital logic
  • Strong communication and team work skills
  • Strong analytical ability, problem solving and communication skills
  • Ability to work independently and at various levels of abstraction
Roles & Responsibilities:
  • Ensuring the logic design meets the architectural specifications
  • Creating and optimizing the validation environment, tools, and methodologies
  • Developing or using checking software to compare model behavior against a specification
  • Generating focused and random test cases, analyzing coverage, and debugging failure cases
  • Analyzing micro-architectural features to identify possible problem areas.
Preferred Education:
Must have a BS or MS in Electrical Engineering, Computer Engineering, or Computer Science
Location:
San Jose, USA
Area of Expertise:
System Verilog – UVM , ARM architecture, AXI/AHB/APB, C++, Perl and Assembly Algorithms and digital logic
Experience:
5+ years of experience in ARM based SOC Verification.
Job Code:
BA-2018-145
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