Openings for Physical Design Engineer

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Basic Qualification:
  • BS + 10yrs or MS + 8yrs in EE/CS
  • 5+ years of experience in ASIC Physical Design from RTL-to-GDSII in either 7nm (must have), 14/16nm, 20nm, or 28nm
  • Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) for synthesis, formal verification, floor planning, bus/pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
  • Scripting experience with Tcl or Perl or Python
Preferred Qualifications:
  • Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
  • Ability to provide mentorship, guidance to junior engineers and be a very effective team player
Preferred Education:
BS/MS in EE/CS
Location:
San Jose, USA
Area of Expertise:
ASIC Physical Design , CAD tools, Tcl or Perl or Python
Experience:
8 to 10 Years
Job Code:
BA-2018-146
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