Openings for Physical Design Engineer

Job Location: Bangalore

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Preferred Qualification:
  • Block level implementation from Netlist to GDS.
  • Handling timing closure of high frequency blocks.
  • Expertise in signoff closure Timing with SI and OCV, Power,IR and Physical Verification at both block and chip level.
  • Understanding constraints and fixing techniques.
  • Understanding SI prevention , fixing methodology and implementation.
  • Proficient in layout edit techniques.
  • Proficient in Synopsys ICC.
  • Experience in Design Automation and UNIX system.
  • Experience in Tcl/Tk, PERL is a plus.
Education:
BE/B.Tech, ME/MTech
Location:
Bangalore, India
Area of Expertise:
Chip level Floorplanning, partitioning, timing budget generation, powerplanning, top PnR, CTS , block integration and ECO generation.
Experience:
4+ Years
Job Code:
BA-2018-172
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