Job Location: Bangalore
- Block level implementation from Netlist to GDS.
- Handling timing closure of high frequency blocks.
- Expertise in signoff closure Timing with SI and OCV, Power,IR and Physical Verification at both block and chip level.
- Understanding constraints and fixing techniques.
- Understanding SI prevention , fixing methodology and implementation.
- Proficient in layout edit techniques.
- Proficient in Synopsys ICC.
- Experience in Design Automation and UNIX system.
- Experience in Tcl/Tk, PERL is a plus.
Area of Expertise:
Chip level Floorplanning, partitioning, timing budget generation, powerplanning, top PnR, CTS , block integration and ECO generation.