Physical Design Engineer

Roles & Responsibilities:
  • Cadence(Cadence Encounter RTL Compiler, Encounter Digital Implementation, Cadence Voltus IC Power Integrity Solution, Cadence Tempus Timing Signoff Solution)
  • Synopsys (Design Compiler, IC Compiler)
  • Magma (BlastFusion, etc.)
  • Mentor Graphics (Olympus SoC, IC-Station, Calibre)
Preferred Education:
B.Tech or BE
Location:
Bengaluru
Area of Expertise:
Floor Planning,CTS,PNR,Timing Analysis,Temous,SOC Encounter,Cadence,Synapse,7NM,10NM,14NM,28NM
Experience:
2+ Years
Job Code:
BA-2017-183
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