Roles & Responsibilities:
- Verification specification
- Verification environment (creation/adaptation/maintenance).
- Test case creation
- Usage of uVC´s
- Development of uVC´s (if needed)
- Usage of reference models (if needed)
- Constrained random testing
- Creation of Coverage matrix
- Writing Verification Reports
Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used.
A successful candidate is an experienced verification engineer with 7 or more years of verification experience.
SV/UVM and/or competence as well as good understanding and knowledge about HW designs are also key factors.
BE/Btech OR ME/Mtech
Area of Expertise: