Roles & Responsibilities:
- Experience in Static Timing Analysis
- Hands on with Prime Time/Gold Time/Design Compiler
- Good at RTL Design/Sign OFF
- Experience in LEC
- Good understanding of ASIC Design flow & Methodologies
- Experience in Timing Analysis at Top & Block levels
BE/B Tech or Higher
Area of Expertise:
STA/Synthesis/Prime Time/Gold Time/Design Compiler
Was this post helpful?
Let us know, if you liked the post. Only in this way, we can improve us.
Powered by Devhats