ASIC Verification

Roles & Responsibilities:
  • Expect the engineers to know programming or scripting in Perl or C/C++. System Verilog and UVM methodology is the basic requirement.
  • Broad exposure with video codecs, image processing, motion detection, AXI bus, Ethernet and other interfaces (no wireless).
  • Most of their verification (80%) is constrained random verification.
  • This is pure verification requirement.
  • Look for 5 to 8 year’s experience
Preferred Education:
B.Tech or BE
Location:
Sweden
Area of Expertise:
Perl or C/C++. System Verilog and UVM
Experience:
5-8 years
Job Code:
BA-2017-181
Was this post helpful?
Let us know, if you liked the post. Only in this way, we can improve us.
Yes0
No0
Powered by Devhats
Contact Us

If you’d like us to contact you, please fill out the form.

Not readable? Change text. captcha txt