Roles & Responsibilities:
- Expect the engineers to know programming or scripting in Perl or C/C++. System Verilog and UVM methodology is the basic requirement.
- Broad exposure with video codecs, image processing, motion detection, AXI bus, Ethernet and other interfaces (no wireless).
- Most of their verification (80%) is constrained random verification.
- This is pure verification requirement.
- Look for 5 to 8 year’s experience
B.Tech or BE
Area of Expertise:
Perl or C/C++. System Verilog and UVM