Roles & Responsibilities:
- Experience in Physical Design Execution
- Experience in block level or chip level Timing closure & Physical Design activities.
- Work independently in the areas of RTL to GDSII implementation
- Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.
- Tcl/Perl scripting
BE/Btech OR ME/Mtech
Area of Expertise:
2 to 12 years
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