Digital ASIC IP verification engineer

Roles & Responsibilities:
The work includes:
  • Design planning
  • Design specification
  • Design implementation
  • Design documentation
  • Design verification (regression + development verification)
  • Miscellaneous tasks in connection to the block design
  • Verification planning
  • Verification specification
  • Verification environment (creation/adaptation/maintenance).
  • Verification documentation
  • Test case creation
  • Usage of uVC´s
  • Usage of reference models (if needed)
  • Constrained random testing

Creation of Coverage matrix

Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used.
A successful candidate is an experienced design & verification engineer with 5 or more years of IP module design &verification (relevant) experience.
Verification shall be done using System Verilog/UVM. The work will be carried out in a cross functional team using Agile ways of working.
Preferred Education:
BE/Btech or ME/Mtech
Area of Expertise:
  • Excellent programming skills (VHDL, SV).
  • Experienced in Hardware design/systemization.
  • Experienced in HW design methodology.
  • Experience of SW design for an embedded environment.
  • Experienced in WCDMA, GSM and/or LTE systems.
  • Experience in system level verification is a plus.
  • Knowledge in using the System Verilog/UVM tools and methodology.
  • Knowledge of verification methodology in general.
  • Knowledge in programming C, C++ and System C.
  • Knowledge about Formal verification is a plus.
  • Knowledge of High Level Synthesis using e.g. the Calypto tool is a plus.
  • Good scripting skills using e.g. Python, TCL and/or Perl.
  • Synthesis and Spyglass.
  • Equivalence check.
  • Knowledge of reference model development.
Knowledge about Agile ways of working is a plus.
7+ years
Job Code:
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