Roles & Responsibilities:
- Design specification
- Design implementation
- Design documentation
- Design verification (regression + development verification)
- Miscellaneous tasks in connection to the block design
- Verification planning
- Verification specification
- Verification environment (creation/adaptation/maintenance).
- Verification documentation
- Test case creation
- Usage of UVC´s
- Usage of reference models (if needed)
- Constrained random testing
- Creation of Coverage matrix
Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used.
A successful candidate is an experienced design & verification engineer with 7 or more years of IP module design &verification (relevant) experience.
Verification shall be done using System Verilog/UVM. The work will be carried out in a cross functional team using Agile ways of working.
BE/Btech OR ME/Mtech
Area of Expertise:
CDC/Lintiq/Lint,RTL Coding using Verilog,Micro architecture