Roles & Responsibilities:
- 3+ years of experience in ASIC design and verification.
- Experience in verifying designs at system level and block level using constrained random verification.
- Expert in System Verilog and UVM based verification.
- Strong experience in ASIC design verification flows and DV methodologies.
- Expert in coding SV Testbench, drivers, monitors, scoreboards, checkers.
- Understanding of AHB, AXI and other bus protocols and system architecture is a plus.
BE/Btech OR ME/Mtech
Area of Expertise:
IP/SoC Verification,System Verilog,UVM
3 to 10 years
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