Design & Verification Engineer with Palladium

Roles & Responsibilities:
MANDATORY – Emulation SOC INTEGRATION Your knowledge base spans from low level programming and detailed design knowledge up to system understanding.
  • Experience in VHDL and Verilog language
  • Experience on Palladium or Veloce synthesis, compilation and debug
  • Experience from HW debugger usage in lab, (e.i. Lauterbach, Green Hill)
  • Experience in Interface modelling for emulation
  • Experience in Test bench design
  • Structured approach to debug and investigation
  • Experienced in C programming.
  • Knowledge in scripting languages (Python, Perl, Linux Shell scripting etc.)
  • Communication and presentation skills in English are essential.
  • Travels may be needed but not required on a frequent basis.
Following experience will be a beneficial asset
  • Knowledge in System Verilog Assertions.
  • Experiences in Formal verification.
  • Knowledge about mobile communication standards.
  • Embedded CPUs (ARM based).
  • Knowledge about several standard interfaces, such as Ethernet, I3C, SPI, SGMII, CPRI etc.
  • Experience from mix-signal design and verification.
Preferred Education:
BE/Btech OR ME/Mtech
Location:
Lund,SWEDEN
Area of Expertise:
SOC Integration,SOC Verification/Emulation,Greenhills,Lauterbach
Experience:
10+ years
Job Code:
BA-2017-160
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