- Comprehensive pre-silicon, post-silicon test planning, test bench development, assertion development, formal verification;
- Understand the analog-digital partition at system level;
- Develop test plan for functional and circuit performance verification;
- develop a scalable test bench using HVLs, test case development, debugging, coverage, model development, coverage closure;
- Work with analog circuit design team, digital design team, analog modelling, characterization team, SoC integration team to complete the successful PHY level verification, integration into SoC, post-silicon validation.
- Bachelor’s degree in Comp. Sc., Engineering (any field) or related field with 5 years of progressive experience as Design Verification Engineer, Sr. Verification Engineer, Design Verification Engineer Trainee or related position.
- Experience in System Verilog, OVM, UVM, USB, AHB and AXI needed. May require travel/relocation to client sites
Bachelor’s degree in Comp. Sc., Engineering (any field)
Location: Santa Clara, CA
Area of Expertise:
System Verilog, OVM, UVM, USB, AHB and AXI
Experience: 5+ Years
Job Code: BA-2016-10