Preferred Education:

• Bachelor’s Degree in Electronics Engineering, Electrical Engineering or a closely related field.

Location:

• CalSoft Labs, Inc., 2890, Zanker Road, Suite 200, San Jose, CA 95134, USA

Contact Person:

• jobsus@altencalsoftlabs.com

Experience:

• BS 3 to 5 years

Roles & Responsibilities:

• Participate in Subsystem partitioning with Module port placement and Block level Floorplan and PnR design with timing, physical DRC fixes.
• Manage Floorplan implementation with all kinds of experiments to meet the required modes for effectiveness (robust power grid with respect to PDN PPA/QOR). 
• Utilize knowledge on all sign-off checks & Fixes (Formal Verification, Conformal Low Power check, Physical Verification, PDN and timing DRC fixes).
• Utilize experience on recent Low-power process nodes (power gating, multi-Vt flow, power supply management, power collapsible design) and high band design.
• Perform STA analysis using Primetime/Tempus and ECO implementation and responsible for fixing DRC’s, ERC, LVS issues.
• Utilize knowledge in fixing design issues like Crosstalk, Electromigration (EM), Signal integrity, Antenna effects, Latchup Timing DRC’s and all Physical verification checks.
• Develop scripts to automate execution tasks as project needs with help of Unix shell and tcl scripting.
• Develop timing constraints and provide feedback based on RTL synthesis. Own IP block level floor planning, CTS and P&R optimizations to meet design specs.
• Define, maintain, and update the generation and validation flow for standard cell physical design collaterals: NDM, LEF, Milkyway, OASIS, OALIB, etc.
• Along with the partition ownership, would be responsible for enhancing/customizing the PD flow & methodology based on the project needs.
• Resolve design and flow issues related to physical design, identify potential solutions, implement timing and functional ECOs, and drive the execution towards the most power efficient implementation.